Foundations and models for the design of on-chip systems and networks
- 2 ECTS
Modern embedded architectures, such as manycore system-on-chips, display an ever increasing amount of parallelism. The efficient allocation of embedded applications onto such platforms then becomes a tricky issue of abstract compilation/synthesis because these applications display themselves an increasing amount of task and data concurrency.
Abstract modeling of all three (application, architecture and allocation - AAA) allows to formulate cleanly the problem, and sometimes to solve it partly in a model-driven engineering framework. In this process, the modeling of the interconnect topology and its behavior, progressively extended to a full on-chip network, plays a central role. Indeed, data communication and transport are becoming the main performance bottleneck for efficiency.
This work programme brings together several existing domains of theoretical and practical computer science, recalled and developed in this course.